1. Field of the Invention
The present invention relates to an alignment mark arrangement and an alignment mark structure and, more particularly, to an alignment mark arrangement and structure which improves wafer alignment contrast.
2. Description of the Prior Art
To fabricate an integrated circuit on a semiconductor substrate such as a wafer, multiple layers of conductors and insulators are patterned and formed upon one another. In order for the devices to perform properly, each circuit pattern must be formed to be aligned as precisely as possible with the circuit pattern that has been previously formed on the wafer.
Typically, the alignment of layers is accomplished using a wafer stepper. The wafer stepper uses a laser beam with a fixed wavelength to sense the position of the alignment mark on the semiconductor wafer. The light from the laser beam is diffracted by the alignment marks, and the diffraction pattern is detected. The relative position of the wafer and the photomask is then adjusted accordingly.
The quality of the diffracted light from the alignment mark is directly related to the structure of the alignment mark, such as the material, the step height or the dimension of the mark.
However, as the wafer has undergone various processes of having circuit patterns formed thereon, the integrity of the alignment mark on the wafer is compromised. For example, the alignment mark may be damaged by abrasive polishing techniques such as chemical mechanical polishing, and the step height of the alignment mark may be reduced or destroyed. If polysilicon or metal silicide or metal layers, which are opaque or reflective, are formed thereon, the alignment mark will become undetectable. When the alignment mark has low reflectivity and insufficient step height, the mark is difficult to be detected. If additional layers are deposited on the mark, the reading of the mark is interfered with.
Various solutions to recover or repair damaged alignment marks have been proposed. For example, forming new alignment marks which do not overlap with the old alignment marks, or forming a mask on the alignment marks to protect the alignment marks from being polished.
However, the solutions mentioned above are time consuming and waste space. Therefore, it would be desirable to reduce the wasted space on the semiconductor wafer and to increase the image contrast of the alignment mark.